ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 1 ? 2004?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. hypertransport is a licensed trademark of the hypertra nsport technology consortium in the u.s. and other jurisdictio ns. all other trademarks are the property of their respective owners. summary the xilinx? automotive (xa) spartan?-3 family of field-programmable gate arrays meets the needs of high-volume, cost-sensitive automotive electronic app lications. the five-member family offers d ensities ranging from 50,000 to 1.5 million system gates, as shown in ta b l e 1 . introduction xa devices are available in both extended-temperature q-grade (?40 c to +125 c t j ) and i-grade (?40 c to +100 c t j ) and are qualified to the industry-recognized aec-q100 standard. the xa spartan-3 family builds on the success of the earlier xa spartan-iie family by increasing the amount of logic resources, the capacity of internal ram, the total number of i/os, and the overall level of performance as well as by improving clock management functions. these spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. because of their exceptionally low cost, spartan-3 fpgas are ideally suited to a wide range of advanced automotive electronics modules and systems ranging from the latest driver assistance and infotain ment systems to instrument clusters and gateways. the spartan-3 family is a fl exible alternative to asics, assps, and microcontrollers. fp gas avoid the high initial nres, the lengthy development cycles, and problems with obsolescence. also, fpga pr ogrammability permits design upgrades in the field with no hardware replacement necessary. features ? aec-q100 device qualification and full ppap documentation support available in both extended temperature q-grade and i-grade ? guaranteed to meet full electrical specification over the t j = ?40 c to +125 c temperature range ? revolutionary 90-nanometer process technology ? low cost, high-performance logic solution for high-volume, automotive applications ? three power rails: for core (1.2v), i/os (1.2v to 3.3v), and auxiliary purposes (2.5v) ? selectio? interface signaling ? up to 487 i/o pins ? 622 mb/s data transfer rate per i/o ? eighteen single-ended signal standards ? eight differential signal standards including lvds ? termination by digitally controlled impedance ? signal swing ranging from 1.14v to 3.45v ? double data rate (ddr) support ? logic resources ? abundant logic cells with shift register capability ? wide multiplexers 0 xa spartan-3 automotive fpga family: introduction and ordering information ds314 (v1.3) june 18, 2009 00 product specification r ta bl e 1 : summary of spartan-3 fpga attributes device system gates logic cells clb array (one clb = four slices) distributed ram (bits 1 ) block ram (bits 1 ) dedicated multipliers dcms maximum user i/o maximum differential i/o pairs rows columns total clbs xa3s50 50k 1,728 16 12 192 12k 72k 4 2 124 56 xa3s200 200k 4,320 24 20 480 30k 216k 12 4 173 76 xa3s400 400k 8,064 32 28 896 56k 288k 16 4 264 116 xa3s1000 1m 17,280 48 40 1,920 120k 432k 24 4 333 149 xa3s1500 1.5m 29,952 64 52 3,328 208k 576k 32 4 487 221 notes: 1. by convention, one kb is equivalent to 1,024 bits.
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 2 r ? fast look-ahead carry logic ? dedicated 18 x 18 multipliers ? jtag logic compatible with ieee 1149.1/1532 ? selectram? hierarchical memory ? up to 576 kbits of total block ram ? up to 208 kbits of total distributed ram ? digital clock manager (up to four dcms) ? clock skew elimination ? frequency synthesis ? high-resolution phase shifting ? maximum clock frequency 125 mhz ? fully supported by xilinx ise? software development system ? synthesis, mapping, placement and routing ? microblaze? processor, can, lin, most, and other cores ? pb-free packaging options ? xilinx and all of our production partners are qualified to iso-ts16949 please refer to the spartan-3 complete data sheet ( ds099 ) for a full product description, ac and dc specifications, and package pinout descriptions architectural overview the spartan-3 family architecture consists of five fundamental programmable functional elements: ? configurable logic blocks (clbs) contain ram-based look-up tables (luts) to implement logic and storage elements that can be used as flip-flops or latches. clbs can be programmed to perform a wide variety of logical functions as well as to store data. ? input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. each iob supports bidirectional data flow plus 3-state operation. twenty-six different signal standards, including eight high-performance differential standards, are available as shown in ta bl e 2 . double data-rate (ddr) registers are included. the digitally controlled impedance (dci) feature provides automatic on-chip terminations, simplifying board designs. ? block ram provides data storage in the form of 18-kbit dual-port blocks. ? multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. ? digital clock manager (dcm) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. these elements are organized as shown in figure 1 . a ring of iobs surrounds a regular array of clbs. the xa3s50 has a single column of block ram embedded in the array. those devices ranging from the xa3s200 to the xa3s1500 have two columns of block ram. each column is made up of several 18 kbit ram blocks; each block is associated with a dedicated multiplier. the dcms are positioned at the ends of the block ram columns. the spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. each functional element has an associated switch matrix that permits multiple connections to the routing.
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 3 r configuration spartan-3 fpgas are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. before powering on the fpga, configuration data is stored externally in a prom or some other nonvolatile medium either on or off the board. after applying power, the configuration data is written to the fpga using any of five different modes: master parallel, slave parallel, master serial, slave serial and boundary scan (jtag). the master and slave parallel modes use an 8-bit-wide selectmap port. i/o capabilities the selectio feature of spartan-3 devices supports 18 single-ended standards and eight differential standards as listed in ta b l e 2 . many standards support the dci feature, which uses integrated terminations to eliminate unwanted signal reflections. ta bl e 3 shows the number of user i/os as well as the number of differential i/o pairs available for each device/package combination. . figure 1: spartan-3 family architecture ds314-1_01_100808 notes: 1. the xa3s50 has only the block ram column on the far left.
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 4 r ta bl e 2 : signal standards supported by the spartan-3 family standard category description v cco (v) class symbol dci option single-ended gtl gunning transceiver logic n/a terminated gtl ye s plus gtlp ye s hstl high-speed transceiver logic 1.5 i hstl_i ye s iii hstl_iii ye s 1.8 i hstl_i_18 ye s ii hstl_ii_18 ye s iii hstl_iii_18 ye s lvcmos low-voltage cmos 1.2 n/a lv c m o s 1 2 no 1.5 n/a lv c m o s 1 5 ye s 1.8 n/a lv c m o s 1 8 ye s 2.5 n/a lv c m o s 2 5 ye s 3.3 n/a lv c m o s 3 3 ye s lvttl low-voltage transistor-transistor logic 3.3 n/a lv t t l no pci peripheral component interconnect 3.0 33 mhz pci33_3 no sstl stub series terminated logic 1.8 n/a (6.7 ma) sstl18_i ye s n/a (13.4 ma) sstl18_ii no 2.5 i sstl2_i ye s ii sstl2_ii ye s differential ldt (ulvds) lightning data transport (hypertransport?) 2.5 n/a ldt_25 no lvds low-voltage differential signaling standard lvds_25 ye s bus blvds_25 no extended mode lvdsext_25 ye s lvpecl low-voltage positive emitter-coupled logic 2.5 n/a lvpecl_25 no rsds reduced-swing differential signaling 2.5 n/a rsds_25 no hstl differential high-speed transceiver logic 1.8 ii diff_hstl_ii_18 ye s sstl differential stub series terminated logic 2.5 ii diff_sstl2_ii ye s
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 5 r dc specifications ta bl e 3 : spartan-3 xa i/o chart device grade available user i/os and differential (diff) i/o pairs vqg100 tqg144 pqg208 ftg256 fgg456 fgg676 user diff user diff user diff user diff user diff user diff xa3s50i,q6329--12456---- - - xa3s200i,q632997461416217376 - - - - xa3s400 i,q - - - - 141 62 173 76 264 116 - - xa3s1000 i,q - - - - - - 173 76 333 149 - - xa3s1500 i - - - - - - - - 333 149 487 221 notes: 1. all device options listed in a given package column are pin-compatible. ta bl e 4 : general recommended operating conditions symbol description min nom max units t j junction temperature i-grade ?40 25 100 c q-grade ?40 25 125 c v ccint internal supply voltage 1.140 1.200 1.260 v v cco (1) output driver supply voltage 1.140 - 3.450 v v ccaux auxiliary supply voltage 2.375 2.500 2.625 v v ccaux (2) voltage variance on vccaux when using a dcm - -10mv/ms v in voltage applied to all user i/o pins and dual-purpose pins relative to gnd v cco = 3.3v ?0.3 - 3.75 v v cco < 2.5v ?0.3 - v cco +0.3 v voltage applied to all dedicated pins relative to gnd ?0.3 - v ccaux + 0.3 v notes: 1. the v cco range given here spans the lowest and highest operating voltages of all supported i/o standards. the recommended v cco range specific to each of the single-ended i/o standards is given in table 34 of ds099 , and that specific to the differential standards is given in table 36 of ds099 . 2. only during dcm operation is it recommended that the rate of change of v ccaux not exceed 10 mv/ms.
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 6 r ordering information spartan-3 fpgas are available in pb-free packaging options for all device/package combinations. the pb-free packages include a special ?g? character in the ordering code. ta bl e 5 : quiescent supply current characteristics symbol description device i-grade maximum q-grade maximum units i ccintq quiescent v ccint supply current xa3s50 50 100 ma xa3s200 125 200 ma xa3s400 180 250 ma xa3s1000 315 400 ma xa3s1500 410 - ma i ccoq quiescent v cco supply current xa3s50 12 12 ma xa3s200 12 12 ma xa3s400 14 14 ma xa3s1000 14 14 ma xa3s1500 16 - ma i ccauxq quiescent v ccaux supply current xa3s50 22 25 ma xa3s200 33 35 ma xa3s400 44 50 ma xa3s1000 55 60 ma xa3s1500 85 - ma notes: 1. the numbers in this table are based on the conditions set forth in table 31 of ds099 . quiescent supply current is measured with all i/o drivers in a high-impedance state and with all pull-up/pull-do wn resistors at the i/o pads disabled. typical values are characterized using devices with typical pr ocessing at ambient room temperature (t a of 25c at v ccint = 1.2v, v cco = 3.3v, and v ccaux = 2.5v). maximum values are the production test limits m easured for each device at the maximum specified junction temperature and at maximum voltage limits with v ccint = 1.26v, v cco = 3.45v, and v ccaux = 2.625v. the fpga is programmed with a ?blank? configuration data file (i.e ., a design with no functional elements inst antiated). for conditions other than tho se described above, (e.g., a design including functional elements, t he use of dci standards , etc.), measured quiescent current lev els may be different than the values in the table. use the xpower power estimator for more accurate estimates. see note 2. 2. there are two recommended ways to estimate the total power consum ption (quiescent plus dynamic) for a specific design: a) the xpower power estimator at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not require a netlist of the design. b) xpower, part of the xilinx ise development so ftware, uses the fpga netlist as input to prov ide more accurate maximum and typical estimates. 3. the maximum numbers in this table also indicate the minimum current each power rail requires in order for the fpga to power-o n successfully, once all three rails are supplied. if v ccint is applied before v ccaux , there may be temporary additional i ccint current until v ccaux is applied. see surplus iccint if vccint applied before vccaux, page 51 of ds099 . figure 2: spartan-3 bga package marking example for part number xa3s1000-4 ftg256q lot code d a te code xa 3s 1000 tm 4q spartan device type bga b a ll a1 p a ck a ge s peed gr a de temper a t u re r a nge r r ftg256egq0525 d12 3 4567a m as k revi s ion code proce ss code f ab ric a tion code d s3 14-1_02_100 8 0 8
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 7 r pb-free packaging for additional information on pb-free packaging, see xapp427 : implementation and solder reflow guidelines for pb-free packages. additional resources ? ds099 , spartan-3 fpga family data sheet ? ug331 , spartan-3 generation fpga user guide ? ug332 , spartan-3 generation configuration user guide revision history the following table shows the revision history for this document: xa3s50 -4 pq g 208 q device type speed grade temperature range: q-grade = automotive extended (t j = ?40c to +125c) i-grade = automotive industrial (t j = ?40c to +100c) package type number of pins pb-free example: ds314-1_03_100808 ta bl e 6 : package types and number of pins device speed grade package type / nu mber of pins temperature range ( t j ) xa3s50 -4 standard performance vqg100 100-pin very thin quad flat pa ck (vqfp) i i-grade (? 40c to +100c) xa3s200 tqg144 144-pin thin quad flat pack (tqfp) q q-grade (? 40c to +125c) xa3s400 pqg208 208-pin plastic quad flat pack (pqfp) xa3s1000 ftg256 256-ball fine-pitch thin ball grid array (ftbga) xa3s1500 fgg456 456-ball fine-pitch ball grid array (fbga) fgg676 676-ball fine-pitch ball grid array (fbga) date version description 10/18/04 1.0 initial xilinx release. 12/20/04 1.1 multiple text edits throughout. 10/27/06 1.2 updated io standards ( ta b l e 2 ), and link to spartan-3 data shee t, added xa3s1500, tqg144, fgg676, ta bl e 4 , and ta b l e 5 . 11/28/06 1.2.1 changed order of explanations in ta bl e 6 for tqg144 and pqg208. 11/12/07 1.2.2 changed all values for the block ram (bits) column and two values for the xa3s1000 row in ta bl e 1 . 01/25/08 1.2.3 changed xa3s1500 q-grade maximum in ta b l e 5 . 06/18/09 1.3 added ug331 and ug332 to "additional resources" section.
introduction and ordering information ds314 (v1.3) june 18, 2009 www.xilinx.com product specification 8 r notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated on the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe, or for use in any applica tion requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. automotive applications disclaimer xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as applicat ions related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. cu stomer assumes the sole risk and liability of any use of xilinx products in such applications.
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